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•Fully automated

•Etch flat and smooth trenches in the backside of a packaged silicon die within a micrometer of the circuit layer

•Metal deposition of long lines and pads for die- and package-level interconnection and test

•Localized trenching preserves the electrical, mechanical and thermal integrity of the IC


  • Full thickness to ultra-thin (< 1 µm) backside preparation of chip-scale, wafer-level, and 3D packaged IC

  • Package removal and circuit edit with copper deposition

Passive voltage contrast imaging in a focused ion beam (FIB) system

Etched Trench in Flip Chip

N-well and shallow trench isolation (STI) layout inside a PLACE created trench on a WLP device

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